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dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Timers/Capture/Compare/PWM:
Interrupt Controller:
? Timer/Counters, up to three 16-bit timers:
- Can pair up to make one 32-bit timer
- One timer runs as Real-Time Clock with
external 32.768 kHz oscillator
- Programmable prescaler
?
?
?
?
?
5-cycle latency
Up to 23 available interrupt sources
Up to three external interrupts
Seven programmable priority levels
Four processor exceptions
? Input Capture (up to three channels):
- Capture on up, down, or both edges
High-Performance MCU CPU Features:
- 16-bit capture input functions
- 4-deep FIFO on each capture
? Output Compare (up to two channels):
- Single or Dual 16-bit Compare mode
- 16-bit Glitchless PWM mode
? Hardware Real-Time Clock and Calendar
(RTCC):
- Provides clock, calendar and alarm function
Digital I/O:
?
?
?
?
?
?
?
?
?
Modified Harvard architecture
C compiler optimized instruction set
16-bit-wide data path
24-bit-wide instructions
Linear program memory addressing up to 4M
instruction words
Linear data memory addressing up to 64 Kbytes
73 base instructions: mostly one word/one cycle
Flexible and powerful indirect addressing mode
Software stack
?
?
?
Peripheral Pin Select functionality
Up to 21 programmable digital I/O pins
Wake-up/Interrupt-on-Change for up to 21 pins
?
?
?
16 x 16 integer multiply operations
32/16 and 16/16 integer divide operations
Up to ±16-bit shifts
?
?
Output pins can drive from 3.0V to 3.6V
Up to 5.5V output with open drain configuration on
5V tolerant pins
Additional High-Performance DSC CPU
Features:
? All digital input pins are 5V tolerant
? Up to 8 mA sink on designated pins
Communication Modules:
? 4-wire SPI:
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
? I 2 C?:
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
? 11 additional instructions
? Two 40-bit accumulators with rounding and
saturation options
? Additional flexible and powerful addressing
modes:
- Modulo
- Bit-reversed
? Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
? Shifts for up to 40-bit data
? 16 x 16 fractional multiply/divide operations
Packaging:
- Slave address masking
? UART:
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
?
?
?
?
?
18-pin PDIP/SOIC
20-pin PDIP/SOIC/SSOP
28-pin SPDIP/SOIC/SSOP/QFN
28-pin QFN: 6x6 mm
36-pin TLA: 5x5 mm
- 4-character TX and RX FIFO buffers
- LIN 2.0 bus support
- IrDA ? encoding and decoding in hardware
- High-Speed mode
- Hardware Flow Control with CTS and RTS
DS70652C-page 4
Note:
Preliminary
See Table 1 for the list of peripheral
features per device.
? 2011 Microchip Technology Inc.
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